Macro-block pin-assignment is an integral step in any Integrated Circuit (IC) physical design and Computer-Aided Design (CAD) tools are often required to handle the design complexity. IC chips include many different components that must have electrical connections there between in order to interoperate. Typically, the chip real estate is divided into different regions with each particular component being assigned a particular region of the “floorplan”.
A technique for establishing pin assignments is to assign the pins manually during floorplanning Routing tools then determine the interconnection routes to connect the respective pins. After determining the routes, a timing analysis is performed to determine if the interconnection routes meet timing constraints. Unfortunately, the timing analysis generally indicates that many of the interconnection routes fail to meet a timing constraint. A consequence of a timing violation is that the initial pin assignments need to be changed. However, once the pin assignments are changed, the routing and timing must be re-performed. Often, it takes many iterations of this cycle before finding satisfactory pin assignments. A consequence of this iteration is that the chip release date is delayed. In today competitive marketplace, time to market is important to the success or failure of a chip.
As chips become more complex and compact, the consequences of pin re-assignments becomes more severe. For example, high performance microprocessors have a substantial amount of custom layout in order to achieve the highest possible performance in the smallest die size. However, re-assigning pins lead to route changes. A possible consequence of routing changes is a need to change the custom layout. Altering a custom layout is very undesirable due to the time, difficulty, and expense. Moreover, changes to a single route can ripple to hundreds of nearby routes, especially if the track routing is dense. Because high performance custom layouts often employ dense routing, the chance of routing changes due to a pin-reassignment is quite high. Because of these and potentially other drawbacks, this approach does not provide wholly satisfactory results. Consequently, an improved method and system for determining the pin assignments for interconnections during an integrated circuit design process is desired.
The enormous complexity of high-performance microprocessor designs in ultra-deep sub-micron technologies and the short time-to-market for the Application Specific Integrated Circuits (ASIC) chips has lead to the adoption and evolution of Computer Aided Design (CAD) tools. The growing size of VLSI designs has also driven the need for hierarchical design methodologies to reduce the overall design turn-around time.
Application Specific Integrated Circuits (ASIC) chips are designed for specific applications or functions such as encoding and decoding digital data, embedded functions within a factory automation system and the like. Generally, ASIC designs adopt a standard cell design methodology wherein the circuit layout for primitive logic operations (AND, OR, NAND, XOR, and the like) are available as a standard cell library that is then used to implement the chip logic function. FIG. 1 illustrates a conventional ASIC design flow, starting with the design specification in a high-level language such as VHDL or Verilog (100), the logic synthesis phase (101) generates a cell-level implementation, i.e. netlist (interconnected cells) that is presented to a physical design to generate a layout mask for chip fabrication. The netlist is then partitioned (102) into blocks based on logic function, physical connectivity or other extraneous design constraints. At this point, the physical design implementation of the partitioned logic is considered subject to fabrication technology, chip package, I/O cells, metal layer stack for interconnect, power distribution and the like. Floorplanning (103) is the phase where the circuit blocks (partitions) are assigned an area, shape and location along with chip I/O cell placement. Once the large blocks are floorplanned, the standard cells are placed and logic optimized, referred to as physical synthesis (104), based on estimated interconnect length. Then, the connections are routed (105) along the shortest length using metal layers on a regular grid (per layer) to complete the chip implementation while meeting the design frequency targets. The generated layout mask (106) captures the geometrical shapes which correspond to the metal, oxide or semiconductor layers that make up the components of the integrated circuit. The layout is then extracted (107) and verified for electrical and functional correctness through simulations (108).
Each phase in the design flow exhibits a flavor of constrained optimization problem, as shown in a typical hierarchical IC design flow (100 to 108, in FIG. 1). For example, logic synthesis (101) attempts to minimize the cell area subject to available library cells (logic functions), delay, power and the like. Partitioning (102) divides the circuit into sub-blocks referred to as macros with a defined physical boundary and macro-block pins serving as the interface for connections from the top (chip) level to the cells within the macros (i.e., connections between cells in different macros and connections between cells and the chip's external pins), wherein the objective is to minimize cuts or interconnect crossings subject to arbitrary cell area balance criteria between the partitions; Floor-planning (103) attempts to shape and place blocks to minimize the estimated interconnect length and chip layout area subject to constraints, such as relative placement of large blocks with respect to I/O cells, spacing of cells, macro-block pin assignment (103) along the periphery of the blocks and alignment to the metal layer pitch. Placement (104) and routing (105) of cells within the macro-blocks and at the chip level have the objective to minimize the routed interconnect length subject to meeting design timing (frequency) and power constraints. A typical VLSI chip design flow presents several inherently hard multi-objective problems that are often divided into sub-problems within each design phase to be solved using CAD tools that employ a combination of optimization techniques and effective heuristics.
Pin-assignment is an integral step in any hierarchical VLSI chip design planning phase and the growing design complexity drives the need for automated solutions that produce good quality of results. However, known pin-assignment algorithms have limitations in that they either use greedy heuristics, or consider nets (pin-connections) sequentially leading to inferior solutions, or create an abstraction for continuous global optimization that ignores detailed pin-placement constraints such as pin-spacing, layer restriction and alignment. Additionally, current methods of macro-block pin assignment require a good deal of manual intervention by a physical design engineer.
Prior literature on pin-assignment relates to different design styles ranging from printed circuit boards to recent multi-million gate integrated circuits (IC) layouts. Broadly, the existing macro-block pin-assignment algorithms can be classified as: i) pin placement on the macros to minimize the estimated top (chip) level wire length, and ii) pin-assignment coupled with global routing on a net-by-net basis. The term net refers to a set of pins (belonging to different standard cells) that are to be connected together.
Broadly, the existing macro-block pin-assignment algorithms can be classified as: i) pin placement on the macros to minimize the estimated top (chip) level wire length, and ii) pin-assignment coupled with global routing on a net-by-net basis. The term net refers to a set of pins (belonging to different cells) that are to be interconnected. More recently, simultaneous pin-assignment and global routing for all two-pin nets using network flow formulation, and pin-placement integrated with analytical cell placement using quadratic programming methods have also been described. However, the known pin-assignment algorithms have limitations in that they use either greedy heuristics, or consider nets (pin-connections) sequentially leading to inferior solutions, or create an abstraction for continuous global optimization that ignores detailed pin-placement constraints such as pin-spacing, layer restriction and alignment. Additionally, current methods of macro-block pin-assignment require a good deal of manual intervention by a physical design engineer.